1. Field of the Invention
The present invention relates to methods of fabricating liquid crystal display (LCD) devices. More particularly, the present invention relates to a method of fabricating integral-type LCD devices incorporating polysilicon-type thin film transistors (TFTs) using a reduced number of mask processes.
2. Discussion of the Related Art
A liquid crystal display (LCD) device generally consists of a display unit capable of displaying images and a driving circuit unit capable of driving the display unit. As such, LCDs may be classified into one of two groups based on the arrangement of the driving circuit unit and the display unit. Driving circuit units of separated-type LCD devices are connected to the display units by a tape carrier package, etc. Driving circuit units of integral-type LCD devices are formed on the same substrate as structures formed on the substrate of the display units, and simultaneously with the formation of the structures formed on the substrate of the display units. Accordingly, the driving circuit units of integral-type LCD devices can be easier to fabricate than driving circuit units of separated-type LCD devices.
Polysilicon is a material having a higher electron mobility than amorphous silicon. Specifically, amorphous silicon has an electron mobility of 0.1˜1 cm2/Vsec while polysilicon, crystallized using an excimer laser, exceeds 100 cm2/Vsec. Therefore, an LCD with a display unit including thin film TFTs having active layers formed of polysilicon, i.e., polysilicon-type TFTs, has a faster response speed than an LCD with a display unit including TFTs with channel layers formed of amorphous silicon, i.e., amorphous-type TFTs. Consequently, LCDs incorporating polysilicon-type TFTs can include more complex circuits and operate at higher speeds than LCDs incorporating amorphous-type TFTs.
FIG. 1 illustrates a schematic view of a related art driving circuit unit of an integral-type LCD device incorporating polysilicon-type TFTs.
Referring to FIG. 1, the driving circuit unit of an integral-type LCD device incorporating polycrystalline-type TFTs consists of a display unit 101 having a plurality of pixels, each comprising a TFT, arranged in a matrix pattern and a driving circuit unit 102 arranged at an peripheral region of the display unit 101 for driving the unit pixels of the display unit 101. The driving circuit unit 102 generally consists of a gate and data drivers 104 and 103, respectively, connected to the unit pixels of the display unit 101, that include p- and n-type TFTs arranged in a complementary metal oxide semiconductor (CMOS) device.
FIGS. 2A to 2I illustrate a related art process of forming an integral-type LCD device incorporating polysilicon-type TFTs.
Referring to FIG. 2A, the related art method of forming an LCD device incorporating polysilicon-type TFTs begins by providing a glass substrate 201 and forming a buffer layer 202 (i.e., an oxidized silicon layer) on the substrate 201 (see FIG. 2A).
Next, an amorphous silicon layer is formed on the buffer layer 202 in a plasma enhanced chemical vapor deposition (PECVD) process at a low temperature followed by a dehydrogenation heat treatment at a temperature of about 400° C. Upon performing the dehydrogenation heat treatment, hydrogen is removed from the amorphous silicon layer to prevent hydrogen within the as-deposited amorphous silicon layer from exploding and damaging the substrate 201 during a subsequently performed crystallization process. The dehydrogenated amorphous silicon layer is then crystallized in a crystallization heat treatment to form a polycrystalline silicon (i.e., polysilicon) layer. One related art process of crystallizing the amorphous silicon layer consists of heating the substrate 201 in an oven. However, the heat involved in this type of crystallization process may deleteriously deform the glass substrate 201. Therefore, another related art process of crystallizing the amorphous silicon layer consists of a laser annealing process. During the laser annealing process, the amorphous silicon layer is quickly melted and allowed to re-solidify. By controlling the temperature gradient within the cooling silicon material, a polysilicon layer having few, but large grains, may be formed. It should be noted that, as the size of the grains increase, the electron mobility of the polysilicon material also increases. After the laser annealing process is performed, the polysilicon layer is dry-etched to define first through third active layers 203a–c (see FIG. 2B), respectively, wherein TFTs of the display unit will be subsequently formed to incorporate the first active layer 203a and TFTs of the driving circuit unit will be subsequently formed to incorporate the second and third active layers 203b and 203c in a CMOS device.
After forming the first through third active layers 203a–c, and with reference to FIG. 2C, a gate insulating layer 204 formed of SiO2 or SiNx, is formed over the entire surface of the substrate 201 to protect the active layers and insulate the active layers from subsequently formed upper layers. Next, a metal layer is formed on the gate insulating layer 204 by a sputtering method and subsequently patterned in a photolithography process to form gate electrodes 205.
Generally, n-type TFTs operate using electrons as charge carriers and, therefore, can generate unacceptable leakage currents. Accordingly, n-type TFTs are beneficially provided as lightly doped drain (LDD)-type TFTs. LDD-type TFTs are formed by implanting n-type impurity ions (e.g., P, As, or other Group V element) into predetermined areas of a source/drain region of an active layer in a low concentration ion implant step (N−) and a high concentration ion implant step (N+).
Referring to FIG. 2D, a first photo mask process (e.g., exposing process, developing process, etc.) is applied to form a first photoresist pattern 206 that shields what will eventually be a p-type TFT region of the driving circuit unit. Next, P ions are implanted at a low concentration into the active layers of what will eventually be n-type TFTs of the driving circuit and display units, wherein gate electrodes 205 exposed by the first photoresist pattern 206 function as an implant mask. Accordingly, a low concentration of n-type ions are implanted into source/drain regions of the first and second active layers 203a and 203b. After the low concentration implant, the first photoresist pattern 206 is removed.
Next, and as shown in FIG. 2E, a second photo mask process is applied to form a second photoresist pattern 207 that shields what will eventually be the p-type TFT as well as the gate electrodes 205 and portions of the source/drain regions of what will eventually be the n-type TFTs. Next, n-type ions are implanted at a high concentration into portions of the first and second active layers 203a and 203b that are exposed by the second photoresist 207, thus forming the n-type TFTs having LDD (low ion concentration) regions 208 and source/drain (high ion concentration) regions 209.
Generally, p-type TFTs operate using holes as charge carriers and, therefore, do not generate leakage currents. Accordingly, p-type TFTs need not be formed as LDD-type TFTs; but, may be formed by implanting p-type impurity ions (e.g., B or other Group III element) into a source/drain region of a active layer.
Referring to FIG. 2F, a second photo mask process is applied to form a third photoresist 210 that exposes only what will eventually be the p-type TFT. Next, B ions are implanted at a high concentration into the active layer of what will eventually be the p-type TFT of the driving circuit unit, wherein the gate electrode 205 exposed by the third photoresist pattern 210 functions as an implant mask. Accordingly, a high concentration of p-type ions are implanted into source/drain regions 211 of the third active layer 203c, thereby forming the p-type TFT. After the high concentration implant, the third photoresist pattern 210 is removed.
Next, and with reference to FIG. 2G, an insulating layer 214 formed of SiO2 or SiNx is deposited on the gate electrodes 205 and contact holes 220 are formed to expose the source/drain regions of the various TFTs. Referring to FIG. 2H, conductive material is be formed within the contact holes 220 to contact the exposed source/drain regions and patterned to form source/drain electrodes 215 and 216.
Referring to FIG. 2I, a passivation layer 217 formed of an organic or inorganic material is deposited over the source/drain electrodes 215 and 216 and a contact hole 219 is formed to expose the drain electrode of the n-type TFT within the display unit. Lastly, a pixel electrode 218 is formed on the passivation layer 217 and within the contact hole 219 to electrically contact the drain electrode 216, thereby completing the LCD device.
The related art process of fabricating integral-type LCD devices incorporating polysilicon-type TFTs described above can be used to produce excellent devices but can be very complicated to perform. Therefore, it would be beneficial to reduce the number of processes required to fabricate integral-type LCD devices incorporating polysilicon-type TFTs.